Metal-oxide-semiconductor (MOS) circuits are widely used in digital large scale integration (LSI) design for digital circuits such as microprocessor and memory circuits. In comparison to bipolar circuits, the MOS circuits allow a more efficient fabrication of transistors on integrated circuit chips. This is because an MOS transistor generally takes up less chip area than a bipolar junction transistor, which means that more transistors can be included in a chip. Consequently, more circuit functions can be performed on the chip with MOS circuits.
One of the most basic digital logic circuits utilizing MOS technology is the conventional inverter. Inverter circuits are so fundamental that, in fact, most MOS logic gates and circuits are derived from the MOS inverter. For instance, logic gates such as AND, NAND, OR, and NOR gates are typically built using the MOS inverters as the basic structure.
These traditional MOS digital logic circuits however, typically suffer from adverse switching noise from individual transistors fabricated onto the integrated circuit chips. In an effort to alleviate the noise problem in MOS integrated circuit chips, prior art MOS logic circuits have been implemented in current-mode structures. The current-mode circuits have the advantage of low digital noise characteristics. For example, in MOS current-mode, the digital switching noise generated by current-mode logic is typically two orders of magnitude smaller than in conventional MOS logic circuits. More background details on current-mode circuits are available from the following publications which are incorporated herein by this reference: Sailesh R. Maskai, et al., Synthesis Techniques for CMOS Folded Source-Coupled Logic Circuits, IEEE Journal of Solid-State Circuits, Vol. 27, No. 8, August 1992; Sayfe Kiaei, et al., CMOS Source-Coupled Logic for Mixed-Mode VLSI, IEEE 1990; and Masayuki Mizuno, et al., A GHz MOS Adaptive Pipeline Technique Using MOS Current-Mode Logic, IEEE Journal of Solid-State Circuits, Vol. 31, No. 6, June 1996.
Due to the low noise characteristics of current-mode structures, integrated circuit chips are increasingly implementing the MOS current-mode logic circuits. Prior Art FIG. 1A illustrates a conventional differential MOS current-mode logic inverter 100. In this inverter circuit 100, a differential pair includes a pair of n-type MOS transistors 102 and 104 coupled to each other on their source terminals. A pair of p-type (e.g., complementary) MOS transistors 118 and 120 are coupled to the drains 110 and 112, respectively, of each transistors 102 and 104, respectively. In this configuration, the transistors 102 and 118 form a branch and the transistors 104 and 120 form another branch. A current source 130 is coupled to the common source terminal of the differential pair (102/104) and provides constant bias current through one of the branches in the circuit 100.
With reference still to Prior Art FIG. 1A, when complementary input voltage signals 106 and 108 are received at the gates of the differential pair (102/104), only one branch conducts current to the current source 130. For example, when the transistor 102 receives high input voltage at its gate, it becomes active and draws current through a diode 126. The current causes a drop in voltage at the drain 110 of the active transistor 102. This corresponds to the low voltage (e.g., inverted voltage), which is buffered by an output transistor 132 biased with a current source 140. The output 136 at the source terminal of the output transistor 132 is a low voltage signal. In contrast, transistors 104 and 120 in the other branch are inactive because the low input voltage 108 at the gate of transistor 104 turns off the transistor 104. Accordingly, only a small leakage current flows through the diode 128 and the transistor 104. As a result, the voltage at the drain 112 of transistor 104 is high (e.g., inverted). An output buffer transistor 134 biased with a current source 142 buffers the voltage at the drain 112 of transistor 104. The output 138 at the source terminal of the output transistor 134 is thus a high voltage signal.
It should be appreciated that the same analysis applies similarly when the differential input signals are reversed. For instance, when the transistor 104 receives high input voltage at its gate, the transistor 102 receives low input voltage. This differential voltage generates a high voltage signal at the output 136 at the source terminal of the output transistor 132 and a low voltage signal at the output 138 at the source terminal of the output transistor 134.
One of the drawbacks of the conventional differential MOS current-mode logic inverter 100 is the switching speed. Specifically, the conventional differential MOS current-mode logic inverter 100 cannot accommodate speeds utilized in some of the latest communication devices, which can require MOS logic circuits to operate up to speeds over 1 gigahertz (GHz). Prior Art FIG. 1B illustrates the relationship between capacitance 160 at the drain node 110 and currents I.sub.1 and I.sub.2 through transistors 102 and 118, respectively. The capacitance 160 is a node capacitance typically associated with a node and may also include parasitic capacitance. The current 12 through the transistor 118 remains constant due to the fixed reference voltage 116 applied at the gate of the transistor 118. In this configuration, when the input voltage 106 at the gate of transistor 102 increases, the voltage at the node 110 decreases and the current I.sub.1 through the transistor 102 increases. Conversely, when the input voltage 106 at the gate of the transistor 102 decreases, the voltage at the node 110 increases and the current I.sub.1 through the transistor 102 decreases. Since the current 12 is constant in either instances, this current is not discharged efficiently to increase the switching speed of the capacitance 160 at the node 110. This same analysis applies in similar manner to the other branch of the circuit comprising transistors 104 and 120.
Prior Art FIG. 1C illustrates a small signal equivalent circuit 150 for one branch comprised of transistors 102 and 118 excluding the diode 126 in the current-mode logic inverter circuit 100 shown in Prior Art FIG. 1A. The gain for this branch is based on the transistor 102 alone and is proportional to g.sub.m1 V.sub.gs1, where g.sub.m1 (e.g., transconductance of transistor 102) is the ratio of output current to the input voltage for transistor 102 and V.sub.gs1 is the voltage between the gate and source of the transistor 102. The resistors, r.sub.O1 and r.sub.O2, represent output resistance of the transistors 102 and 118, respectively. The complementary MOS transistor 118 does not contribute to the gain because V.sub.gs1 of the transistor 118 is fixed to a fixed voltage, Vref 116. Hence, the overall small signal gain for the branch is relatively low. It should be appreciated that the same analysis applies similarly to the other branch of the circuit comprising transistors 104 and 120.
The low gain affects the switching speed of the transistors in the current-mode logic circuit. Since g.sub.m is defined as the ratio of output current to the input voltage, it is directly proportional to the output current. If the output current is increased, the gain increases. Typically, inverter circuits have capacitance that allows charging and discharging of currents. When current is increased, the capacitance charges and discharges at a faster rate. Hence, the switching speed increases when gain increases. It would be advantageous to increase the switching speed of circuit 100.
Thus, what is needed is a differential CMOS current-mode logic circuit with higher gain and speed. Accordingly, the present invention satisfies these needs by providing a high speed and gain differential CMOS current-mode logic circuit.